//********************************
//******* zhoudaoxi **************
//********************************
module	AUPP8_TOP(
	reset,
	clk155m_sys,rx_clk155m,

	//******
	fp_in,
	data_in,

	fp_pi_out,
	j1_pi_out,
	spe_pi_out,
	data_pi_out,

	//******
	fp_ppfa_regen,

	fp_pr_out,
	j1_pr_out,
	spe_pr_out,
	data_pr_out,

	//******
	hp_fifo_ovf_1,	hp_fifo_ovf_2,	hp_fifo_ovf_3,	hp_fifo_ovf_4,
	ptr_itpre_st1,	ptr_itpre_st2,	ptr_itpre_st3,	ptr_itpre_st4,
	ptr_itpre_st5,	ptr_itpre_st6,	ptr_itpre_st7,	ptr_itpre_st8,
	ptr_regen_st,
	h1_pos_y1
	);
//*************************
//*************************
input			reset;
input			clk155m_sys,rx_clk155m;

//******
input			fp_in;
input	[7:0]	data_in;

output			fp_pi_out;
output			j1_pi_out;
output			spe_pi_out;
output	[7:0]	data_pi_out;

//******
input			fp_ppfa_regen;

output			fp_pr_out;
output			j1_pr_out;
output			spe_pr_out;
output	[7:0]	data_pr_out;

//******
output			hp_fifo_ovf_1;
output			hp_fifo_ovf_2;
output			hp_fifo_ovf_3;
output			hp_fifo_ovf_4;
(* keep = "TRUE" *)output	[1:0]	ptr_itpre_st1,ptr_itpre_st2,ptr_itpre_st3,ptr_itpre_st4;
(* keep = "TRUE" *)output	[1:0]	ptr_itpre_st5,ptr_itpre_st6,ptr_itpre_st7,ptr_itpre_st8;
output	[2:0]	ptr_regen_st;
output			h1_pos_y1;

//***************************
//***************************
wire			fp_pi_out;
wire			j1_pi_out;
wire			spe_pi_out;
wire	[7:0]	data_pi_out;

wire	[9:0]	waddr_pl;
wire	[8:0]	wdata_pl;
wire			wen_pl;
wire	[1:0]	ptr_itpre_st1;
wire	[1:0]	ptr_itpre_st2;
wire	[1:0]	ptr_itpre_st3;
wire	[1:0]	ptr_itpre_st4;
wire	[1:0]	ptr_itpre_st5;
wire	[1:0]	ptr_itpre_st6;
wire	[1:0]	ptr_itpre_st7;
wire	[1:0]	ptr_itpre_st8;

wire	[4:0]	waddr_pl_h_t1;
wire	[4:0]	waddr_pl_h_t2;
wire	[4:0]	waddr_pl_h_t3;
wire	[4:0]	waddr_pl_h_t4;
wire	[4:0]	waddr_pl_h_t5;
wire	[4:0]	waddr_pl_h_t6;
wire	[4:0]	waddr_pl_h_t7;
wire	[4:0]	waddr_pl_h_t8;

wire	[2:0]	pi_chan_y3;

wire			fp_pr_out;
wire			j1_pr_out;
wire			spe_pr_out;
wire	[7:0]	data_pr_out;
wire	[9:0]	raddr_pl;
wire	[8:0]	rdata_pl;


//*************************
//***************************
AU8_ITPRE	U_AU_ITPRE(
		.reset			(reset),
		.rx_clk155m		(rx_clk155m),
	
		.fp_to_ppfa		(fp_in),
		.data_to_ppfa	(data_in),
		
		.fp_out			(fp_pi_out),
		.j1_out			(j1_pi_out),
		.spe_out		(spe_pi_out),
		.data_out		(data_pi_out),
		
		.waddr_pl		(waddr_pl),
		.wdata_pl		(wdata_pl),
		.wen_pl			(wen_pl),

		.ptr_itpre_st1	(ptr_itpre_st1),
		.ptr_itpre_st2	(ptr_itpre_st2),
		.ptr_itpre_st3	(ptr_itpre_st3),
		.ptr_itpre_st4	(ptr_itpre_st4),
		.ptr_itpre_st5	(ptr_itpre_st5),
		.ptr_itpre_st6	(ptr_itpre_st6),
		.ptr_itpre_st7	(ptr_itpre_st7),
		.ptr_itpre_st8	(ptr_itpre_st8),
		
		.waddr_pl_h_t1	(waddr_pl_h_t1),
		.waddr_pl_h_t2	(waddr_pl_h_t2),
		.waddr_pl_h_t3	(waddr_pl_h_t3),
		.waddr_pl_h_t4	(waddr_pl_h_t4),
		.waddr_pl_h_t5	(waddr_pl_h_t5),
		.waddr_pl_h_t6	(waddr_pl_h_t6),
		.waddr_pl_h_t7	(waddr_pl_h_t7),
		.waddr_pl_h_t8	(waddr_pl_h_t8),
		.pi_chan_y3		(pi_chan_y3)
		);

//AU8_RAM1Kx9 U_RAM1Kx9(
//		.wrclock		(rx_clk155m),
//		.wren			(wen_pl),
//		.wraddress		({waddr_pl}),
//		.data			(wdata_pl),
		
//		.rdclock		(clk155m_sys),
//		.rdaddress		({raddr_pl}),
//		.q				(rdata_pl)
//		);

AU8_RAM1Kx9                     U_RAM1Kx9(
   .clka                        ( rx_clk155m ),
   .wea                         ( wen_pl ),
   .addra                       ( waddr_pl ),
   .dina                        ( wdata_pl ),
   .clkb                        ( clk155m_sys ),
   .addrb                       ( raddr_pl ),
   .doutb                       ( rdata_pl )
   );


AU8_REGEN	U_AU_REGEN(
		.reset			(reset),
		.clk155m_sys	(clk155m_sys),

		.fp_ppfa_regen	(fp_ppfa_regen),
		
		.pl_ais_force	(1'b0),
		.ptr_itpre_st1	(ptr_itpre_st1),
		.ptr_itpre_st2	(ptr_itpre_st2),
		.ptr_itpre_st3	(ptr_itpre_st3),
		.ptr_itpre_st4	(ptr_itpre_st4),
		.ptr_itpre_st5	(ptr_itpre_st5),
		.ptr_itpre_st6	(ptr_itpre_st6),
		.ptr_itpre_st7	(ptr_itpre_st7),
		.ptr_itpre_st8	(ptr_itpre_st8),
		
		.waddr_pl_h_t1	(waddr_pl_h_t1),
		.waddr_pl_h_t2	(waddr_pl_h_t2),
		.waddr_pl_h_t3	(waddr_pl_h_t3),
		.waddr_pl_h_t4	(waddr_pl_h_t4),
		.waddr_pl_h_t5	(waddr_pl_h_t5),
		.waddr_pl_h_t6	(waddr_pl_h_t6),
		.waddr_pl_h_t7	(waddr_pl_h_t7),
		.waddr_pl_h_t8	(waddr_pl_h_t8),
		.pi_chan_y3		(pi_chan_y3),
		
		.raddr_pl		(raddr_pl),
		.rdata_pl		(rdata_pl),
		
		.fp_to_pohp		(fp_pr_out),
		.j1_to_pohp		(j1_pr_out),
		.spe_to_pohp	(spe_pr_out),
		.data_to_pohp	(data_pr_out),
		.hp_fifo_ovf_1	(hp_fifo_ovf_1),
		.hp_fifo_ovf_2	(hp_fifo_ovf_2),
		.hp_fifo_ovf_3	(hp_fifo_ovf_3),
		.hp_fifo_ovf_4	(hp_fifo_ovf_4),
		.ptr_regen_st	(ptr_regen_st),
		.h1_pos_y1		(h1_pos_y1)
		);

	
endmodule